1. Field of the Invention
The present invention relates to synchronous control apparatus and method for generating an output signal of a frequency in synchronism with data received from an external apparatus.
2. Prior Art
Conventionally, a PLL (phase-locked loop) circuit is known as a means for generating an output signal of a frequency in synchronism with an input signal. A general PLL circuit is principally comprised of a phase comparator that compares the phase of the input signal with that of an output signal (such as a reproduced clock signal), a loop filter that smoothes the output of the comparator, and a VCO (voltage-controlled oscillator) that generates a reproduced clock signal whose frequency varies depending upon the output of the loop filter. In the case where a sampling clock signal of 44.1 kHz is reproduced from an input signal of 1 kHz so that the sampling clock signal is in phase with the input signal, for example, a frequency divider circuit needs to be provided in a feedback path leading to the phase comparator, for reducing the frequency (44 kHz) of the sampling clock signal to be reproduced, down to 1 kHz.
In the conventional PLL circuit, however, all of its components or elements must be physically constructed using hardware, and therefore the number of components used in the circuit increases particularly with an increase in the number of stages of the frequency divider (frequency divider ratio), resulting in a rather complicated circuit configuration. Also, a pull-in response (response to an input signal) of the conventional PLL circuit depends upon the time constant of the loop filter, and, since the time constant cannot be easily changed, it takes time to pull in or capture the input signal (i.e., input signal processing) if the frequency of the input signal is largely different from that of the output signal. Furthermore, since circuit components are built in the conventional (PLL) circuit assuming a particular input/output frequency ratio, the PLL circuit is unable to flexibly deal with input and output signals having different frequency ratios.
It is therefore a first object of the present invention to provide a synchronous control apparatus which has a simple circuit configuration and ensures a sufficiently high pull-in speed, and which is able to flexibly handle input and output signals having different frequency ratios.
It is a second object to provide such a synchronous control method.
To attain the first object, the present invention provides a synchronous control apparatus comprising a digital variable-frequency oscillator having an output frequency thereof variable in dependence upon a frequency control variable, a data storage device that stores externally input data, and generates the data in accordance with an output of the digital variable-frequency oscillator, and a control device that controls the output frequency of the digital variable-frequency oscillator, by detecting a remaining data amount of the data storage device in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal, calculating a new value of the frequency control variable based on a difference between the detected remaining data amount of the data storage device and a target data amount thereof, and controlling the output frequency of the digital variable-frequency oscillator based on the calculated new value of the frequency control variable so as to reduce a difference between the remaining data amount of the data storage device and the target data amount thereof.
In a preferred form of the invention, the synchronous control apparatus comprises a digital variable-frequency oscillator having an output frequency thereof variable in dependence upon a frequency control variable, a data storage device that stores externally input data, and generates the data in accordance with an output of the digital variable-frequency oscillator, and a control device that controls the output frequency of the digital variable-frequency oscillator, by detecting a remaining data amount of the data storage device in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal, performing a filtering operation on values of the frequency control variable so as to calculate an average value of the frequency control variable, calculating a new value of the frequency control variable based on the calculated average value and a difference between the detected remaining data amount of the data storage device and a target data amount thereof, and controlling the output frequency of the digital variable-frequency oscillator based on the calculated new value of the frequency control variable so as to reduce a difference between the remaining data amount of the data storage device and the target data amount thereof.
Preferably, the control device performs the filtering operation on a difference between a previous value of the frequency control variable and a previous average value of the frequency control variable, so as to calculate a current average value of the frequency control variable, and calculates the new value of the frequency control variable based on the current average value and the difference between the detected remaining data amount and the target data amount.
Also preferably, the control device determines an output value based on a curve of at least the second order from the difference between the detected remaining data amount of the data storage device and the target data amount, and calculates the new value of the frequency control variable based on the calculated average value of the frequency control variable and the determined output value.
More preferably, the control device includes an inhibiting device that inhibits the frequency control variable from being changed when the difference between the detected remaining data amount of the data storage device and the target data amount is within a predetermined permissible fluctuation range while the synchronous control circuit is in a locked state.
Preferably, the target data amount is set to one half of a capacity of the data storage device.
To attain the second object, the present invention provides a synchronous control method comprising the steps of generating a sampling signal having a frequency thereof variable in dependence upon a frequency control variable, storing externally input data in a data storage device, and generating the data in accordance with the sampling signal, detecting a remaining data amount of the data storage device in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal, calculating a new value of the frequency control variable based on a difference between the detected remaining data amount of the data storage device and a target data amount thereof, and controlling the frequency of the sampling signal based on the calculated new value of the frequency control variable so as to reduce a difference between the remaining data amount of the data storage device and the target data amount thereof.
In a preferred form of the invention, the synchronous control method comprises the steps of generating a sampling signal having a frequency thereof variable in dependence upon a frequency control variable, storing externally input data in a data storage device, and generating the data in accordance with the sampling signal, detecting a remaining data amount of the data storage device in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal, performing a filtering operation on values of the frequency control variable so as to calculate an average value of the frequency control variable, calculating a new value of the frequency control variable based on the calculated average value and a difference between the detected remaining data amount of the data storage device and a target data amount thereof, and controlling the frequency of the sampling signal based on the calculated new value of the frequency control variable so as to reduce a difference between the remaining data amount of the data storage device and the target data amount thereof.
In the synchronous control apparatus and method of the present invention constructed as described above, while the data storage device outputs data in accordance with the output of the digital variable-frequency oscillator, the control device checks the amount of data remaining in the storage device upon an input of each pulse of the externally input timing signal based on which synchronizing operations are performed. The control device calculates a new value of the frequency control variable, depending upon which the output frequency of the digital variable-frequency oscillator is variable, based upon a difference between the checked or detected remaining data amount of the data storage device and a target data amount. Preferably, after performing a filtering operation on values of the frequency control variable, so as to obtain an average value of the frequency control variable, a new value of the frequency control variable is calculated based on the calculated average value and a difference between the checked or detected remaining data amount of the data storage device and a target data amount. Based on the thus calculated frequency control variable, the control device controls the output frequency of the digital variable-frequency oscillator so as to reduce or minimize the difference between the remaining data amount of the data storage device and the target data amount.
According to the present invention, therefore, checking or detecting of the remaining data amount, calculation of the difference between the detected remaining data amount and the target data amount, filtering operation, and calculation of the control variable of the digital variable-frequency oscillator can be all realized by software, and thus the required number of components can be significantly reduced. Also, a variation or deviation in the output frequency of the digital variable-frequency oscillator in either positive or negative direction can be directly obtained based on the difference between the remaining data amount and the target data amount, thus permitting the apparatus to accomplish a quick frequency pull-in operation in order to absorb or minimize the deviation. Furthermore, according to the present invention, the filtering operation is performed for calculation of the frequency control variable, which is advantageous in terms of stabilization of the circuit system.
Further, the value of the frequency control variable may be calculated based on a curve of the second or higher order that represents a relationship of the frequency control variable with the difference between the remaining data amount and the target data amount. In this case, the pull-in response speed (response to the input signal) is further improved. Also, the control device is preferably inhibited from changing the value of the frequency control variable when the difference between the remaining data amount and the target data amount is within a predetermined permissible fluctuation range. With this arrangement, varying frequency components due to jitter of the input data can be driven away into a low frequency region outside the audible frequency band, assuring improved audio characteristics.